Addressing Resiliency of In-Memory Floating Point Computation
Addressing Resiliency of In-Memory Floating Point Computation
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DOI：
10.1109/tvlsi.2022.3170542
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发表时间：
2020-11
影响因子：
2.8
通讯作者：
Sina Sayyah Ensan;Swaroop Ghosh;Seyedhamidreza Motaman;Derek Weast
中科院分区：
文献类型：
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作者：
Sina Sayyah Ensan;Swaroop Ghosh;Seyedhamidreza Motaman;Derek Weast
内存计算（IMC）可以消除处理器和内存之间的数据移动，这是冯诺依曼计算的能量效率和性能的障碍。电阻式随机存取存储器（RRAM）具有功耗低、运行速度快、占用空间小等优点，是内模控制应用中最有前途的器件之一。我们提出FPCAS，流水线浮点（FP）算术（加/减）求解器的基础上RRAM交叉。虽然有希望，但基于RRAM的计算可能会遇到随机故障，例如RRAM单元卡在高电阻状态（HRS），即，固定在0（SA 0）或低电阻状态（LRS），即，Stuck-at-1（SA1）。我们提出的技术，以防止SA 1故障，即，移位在输出端（SATO），力到$V_{\mathrm{ DD}}$（FTV），和力到地（FTG），因为96%的RRAM在我们的架构中采用HRS。使用额外的时钟周期，这两种策略都采用存储器阵列的无故障RRAM来进行计算。当故障率小于2%时，SATO可以处理70%以上的故障，而FTV可以在低功率和低面积开销的情况下处理90%以上的故障。仿真结果表明，对于基于$\mathrm{\scriptstyle NAND}$ - $\mathrm{\scriptstyle NAND}$和$\mathrm{\scriptstyle NOR}$ - $\mathrm{\scriptstyle NOR}$的实现，FPCAS分别消耗335和322 pJ。这两种实现方式在阵列级的性能开销为50%，在流水线FP实现中为4%。
In-memory computing (IMC) can eliminate data movement between processor and memory, which is a barrier to the energy efficiency and performance in von Neumann computing. Due to low power consumption, fast operation, and tiny footprint in crossbar architecture, resistive RAM (RRAM) is one of the most promising devices for IMC applications. We present FPCAS, a pipelined floating point (FP) arithmetic (addition/ subtraction) solver based on RRAM crossbars. Although promis- ing, RRAM-based computing may experience random failures, such as the stuck-at fault where RRAM cells are stuck at either a high-resistance state (HRS), i.e., stuck-at-0 (SA0), or a low-resistance state (LRS), i.e., stuck-at-1 (SA1). We propose techniques to prevent SA1 failures, namely, shifting-at-the-output (SATO), force to $V_{\mathrm{ DD}}$ (FTV), and force to ground (FTG) since 96% of the RRAMs employed in our architecture are in HRS. Using an extra clock cycle, both strategies employ the memory array’s fault-free RRAMs to conduct the computation. When the failure rate is less than 2%, SATO can manage more than 70% of faults, whereas FTV can handle more than 90% of faults at low power and low area overhead. Simulation results reveal that, for $\mathrm{\scriptstyle NAND}$ – $\mathrm{\scriptstyle NAND}$ - and $\mathrm{\scriptstyle NOR}$ – $\mathrm{\scriptstyle NOR}$ -based implementations, FPCAS consumes 335 and 322 pJ, respectively. Both implementations incur a performance overhead of 50% at the array level and 4% for pipelined FP implementation.