High-voltage drain extended MOS transistors for 0.18-/spl mu/m logic CMOS process
High-voltage drain extended MOS transistors for 0.18-/spl mu/m logic CMOS process
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DOI：
10.1109/16.936703
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发表时间：
2001-08
影响因子：
3.1
通讯作者：
J. Mitros;Chin-Yu Tsai;H. Shichijo;M. Kunz;A. Morton;D. Goodpaster;D. Mosher;T. Efland
中科院分区：
文献类型：
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作者：
J. Mitros;Chin-Yu Tsai;H. Shichijo;M. Kunz;A. Morton;D. Goodpaster;D. Mosher;T. Efland
互补高压漏极扩展（DE）MOS晶体管采用了Texas Instruments最先进的模拟和数字1.5-1.8 V CMOS技术。这些晶体管允许5 V的漏极工作电压使用的核心栅极氧化物，并具有漏极击穿电压BV/sub dss/>10 V的实验结果沿着Suprem 4和MEDICI的模拟结果来解释他们的操作。新型p沟道晶体管使用隔离补偿p阱作为漏极扩展。n沟道版本使用n阱作为漏极扩展。I/sub ds/（V/sub ds/，V/sub gs/）、I/sub gs/（V/sub ds/）和BV（L）曲线的实验测试结果证明了DE-MOS性能。这项工作的重点是性能优化与零工艺修改，因此没有成本加法器。
Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology. These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages BV/sub dss/>10 V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of I/sub ds/(V/sub ds/,V/sub gs/), I/sub gs/(V/sub ds/), and BV(L) plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no cost adder.