Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS
Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS
复制标题
在 55 nm DDC CMOS 中使用无放大器复制偏置开关技术的基于低压栅极泄漏的定时器
DOI：
10.1109/ojcas.2020.3007393
复制
发表时间：
2020
影响因子：
2.6
通讯作者：
Niitsu Kiichi
中科院分区：
文献类型：
--
作者：
Kobayashi Atsuki;Niitsu Kiichi
在执行测量和数据通信等周期性操作的许多应用中，都需要高能效的定时器电路。在本文中，我们提出了一种基于门泄漏的定时器，它利用一种无放大器的复制偏置开关技术来产生稳定的频率，该频率可以在低电源电压下工作。为了在较小的电路面积内保证稳定的振荡频率，该设计采用了一种通过带有低泄漏开关的阻性元件(漏极漏极MOS电容器)对预充电电容器进行放电的结构。在所提出的开关技术中，低电压定时器通过跟踪电容器的放电端并偏置开关单元的参考电压来操作，从而能够在不需要模拟放大器电路的情况下最小化泄漏电流。定时器的高电源灵敏度通过使用本地NMOS接口(NNH)调节电源电压来解决。该设计采用55 nm深度耗尽沟道工艺制造，具有很强的体系数，占用的有源电路面积为0.0022 mm2。测试结果表明，在350 mV的电源电压下，当施加体偏压时，所提出的设计可以达到25pJ/周期的能量值。在室温下测得的Allan偏差下限为200ppm。该定时器对四个样品的平均温度灵敏度为810ppm/°C。此外，在0.0034 mm~2的有源电路面积内，使用nnh可将电源灵敏度降低26倍。
Energy-efficient timer circuits are required in numerous applications for periodic operations, such as performing measurements and communicating data. In this paper, we present a gate-leakage-based timer that utilizes an amplifier-less replica-bias switching technique to generate a stable frequency, which can operate at a low supply voltage. To guarantee a stable oscillation frequency in a small circuit area, the proposed design adopts an architecture that discharges a pre-charged capacitor through a resistive element (gate-leaking MOS capacitor) with a low-leakage switch. In the proposed switching technique, the low-voltage timer operates by tracking the discharging terminal of the capacitor and biasing the reference voltage of the switch unit, thereby enabling the minimization of the leakage current without the need for analog amplifier circuits. The high supply sensitivity of the timer is addressed by regulating the supply voltage using a native NMOS header (NNH). The proposed design is fabricated using the 55-nm deeply depleted channel (DDC) CMOS technology, which has a strong body coefficient and occupies an active circuit area of 0.0022 mm2. The measurements show that the proposed design can achieve an energy-per-cycle value of 25 pJ/cycle at a supply voltage of 350 mV when body biasing is applied. The measured Allan deviation floor is 200 ppm at room temperature. The timer exhibits an average temperature sensitivity of 810 ppm/°C for four samples. Moreover, a reduction in the supply sensitivity by a factor of 26 using the NNH is demonstrated in an active circuit area of 0.0034 mm2.