18.4 A 0.55nW/0.5V 32kHz Crystal Oscillator Based on a DC-Only Sustaining Amplifier for IoT

18.4 A 0.55nW/0.5V 32kHz Crystal Oscillator Based on a DC-Only Sustaining Amplifier for IoT
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用于物联网的基于纯直流维持放大器的 18.4 A 0.55nW/0.5V 32kHz 晶体振荡器

DOI:
10.1109/isscc.2019.8662383
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发表时间:
2019
期刊:
2019 IEEE International Solid- State Circuits Conference - (ISSCC)
影响因子:
--
通讯作者:
S. Pamarti
S. Pamarti
中科院分区:
--
文献类型:
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作者:
H. Esmaeelzadeh;S. Pamarti

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始终开启、稳定的 32kHz 晶体振荡器 (XO) 在大多数电子系统中提供关键的计时、同步和睡眠定时器功能。 XO 的超低功耗 (ULP) 对于物联网 (IoT) 等高占空比、能源受限的系统至关重要。传统的 XO 通常采用 Pierce 配置,功耗为 10 至 100nW:需要足够大的跨导 $g_{m}\, \gt \omega _{O}^{2} {\cdot C}_{L}^{2} {\cdot R}_{m}$ 来补偿晶体运动电阻 $R_{m}$ 的损耗,并维持频率 $\omega 的振荡_{O}$,跨负载电容器 $(C_{L}\, \gt 15$ pF,图 18.4.1),这些电容器不可避免地很大,以确保工艺、电压和温度 (PVT) 变化时的频率稳定性。最近的 32kHz XO 设计报告了低于 10nW 的功耗 [1] - [4],方法是对维持放大器进行占空比 [4],或者仅通过 XO 波形峰值处的窄脉冲提供能量来补偿晶体损耗 [1] - [3]。然而,它们需要高功率组件 [2]、具有多个功率域 [1]-[2] 的复杂设计来正确定时脉冲,或者需要大量校准和片外组件 [4] 以降低 PVT 灵敏度。
An always-ON, stable, 32kHz crystal oscillator (XO) provides key time-keeping, synchronization, and sleep-timer functions in most electronic systems. Ultra-low power (ULP) consumption of the XO is critical in highly duty-cycled, energy-constrained systems such as Internet-of-things (IoT). Conventional XOs, typically implemented in the Pierce configuration, consume 10 to 100nW: a large enough transconductance, $g_{m}\, \gt \omega _{O}^{2} {\cdot C}_{L}^{2} {\cdot R}_{m}$, is needed to compensate for loss in the crystal’s motional resistance, $R_{m}$, and sustain oscillations at frequency $\omega _{O}$, across load capacitors $(C_{L}\, \gt 15$ pF in Fig. 18.4.1) that are inevitably large to ensure frequency stability over process, voltage, and temperature (PVT) variations. Recent 32kHz XO designs report sub-10nW power consumption [1] –[4] by either duty-cycling the sustaining amplifier [4] or by providing energy to compensate the crystal losses only via narrow pulses at the peaks of the XO waveform [1]–[3]. However, they require high-power components [2], complicated designs with multiple power domains [1]–[2] to properly time the pulses, or significant calibration and off-chip components [4] to reduce PVT sensitivity.