Timed trace theoretic verification using partial order reduction
Timed trace theoretic verification using partial order reduction
复制标题
使用偏序约简的定时迹理论验证
DOI：
10.1109/async.1999.761527
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
Hiroshi Ryu
中科院分区：
文献类型：
--
作者：
T. Yoneda;Hiroshi Ryu
本文对偏序降阶的迹论验证方法进行了扩展，使其能够很好地处理时序电路和时序规范。偏序降阶算法是从固执集法的时间版本中得到的。对STARI电路的实验结果表明，该方法是非常有效的。
In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.