A HIERARCHICAL COMPILED CODE EVENT-DRIVEN LOGIC SIMULATOR
A HIERARCHICAL COMPILED CODE EVENT-DRIVEN LOGIC SIMULATOR
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DOI：
10.1109/43.137501
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发表时间：
1991-06-01
影响因子：
2.9
通讯作者：
LEWIS, DM
中科院分区：
文献类型：
--
作者：
LEWIS, DM
本文介绍了减少单元延迟逻辑仿真的预处理时间和执行时间的逻辑仿真技术。使用线程代码组织的编译代码实现技术应用于事件驱动的逻辑模拟算法。与传统的事件驱动仿真相比，该技术将仿真速度提高了10倍。然后将该技术扩展到分层仿真，其中为每个独特的模块生成扇出过程和仿真过程。分层模拟减少了预处理时间，并且只允许重新编译那些被修改的模块。模拟器使用便携式机器模型，其中的体系结构文件描述目标机器。通过定义架构，模拟器可以快速移植到新机器上，同时仍然获得高性能。
This paper describes logic simulation techniques that reduce both preprocessing time and execution time of unit delay logic simulation. Compiled code implementation techniques using a threaded code organization are applied to the event driven logic simulation algorithm. Simulation speed is increased by a factor of up to 10 by this technique compared to conventional event-driven simulation. This technique is then extended to hierarchical simulation, in which a fan-out procedure and simulation procedure is generated for each unique module. Hierarchical simulation reduces preprocessing time and allows the recompilation of only those modules that are modified.The simulator uses a portable machine model, in which an architecture file describes the target machine. The simulator can be quickly ported to new machines by defining the architecture, while still obtaining high performance.