FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro
FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro
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DOI：
10.1109/esscirc59616.2023.10268770
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发表时间：
2023-09
期刊：
影响因子：
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通讯作者：
Jyotishman Saikia;Amitesh Sridharan;Injune Yeo;S. Venkataramanaiah;Deliang Fan;J.-s. Seo
中科院分区：
文献类型：
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作者：
Jyotishman Saikia;Amitesh Sridharan;Injune Yeo;S. Venkataramanaiah;Deliang Fan;J.-s. Seo
内存计算（IMC）为深度神经网络（DNN）提供了节能解决方案。DNN的大多数IMC设计采用定点精度。然而，DNN训练和复杂的推理模型仍然需要浮点精度来保持高精度。在文献中还没有基于浮点精度的IMC作品，其中浮点计算浸入到权重存储器中。在这项工作中，我们提出了一种新型的浮点精度IMC宏，具有可配置的架构，支持普通8位浮点（FP 8）和具有共享指数的8位块浮点（BF 8）。在2Snm CMOS中实现的FP-IMC宏在FPS精度下表现出12.1 TOPS/W，在BFS精度下表现出66.6 TOPS/W，提高了能效，超过了最先进的FP IMC宏。
In-memory computing (IMC) provides energy-efficient solutions to deep neural networks (DNN). Most IMC designs for DNNs employ fixed-point precisions. However, floatingpoint precision is still required for DNN training and complex inference models to maintain high accuracy. There have not been float-point precision based IMC works in the literature where the float-point computation is immersed into the weight memory storage. In this work, we propose a novel floating-point precision IMC macro with a configurable architecture that supports both normal 8-bit floating point (FP8) and 8-bit block floating point (BF8) with a shared exponent. The proposed FP-IMC macro implemented in 2Snm CMOS demonstrates 12.1 TOPS/W for FPS precision and 66.6 TOPS/W for BFS precision, improving energy-efficiency beyond the state-of-the-art FP IMC macros.