On Selecting Testable Paths in Scan Designs
On Selecting Testable Paths in Scan Designs
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DOI：
10.1109/etw.2002.1029639
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发表时间：
2002-11
期刊：
影响因子：
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通讯作者：
Yun Shao;S. Reddy;I. Pomeranz;S. Kajihara
中科院分区：
文献类型：
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作者：
Yun Shao;S. Reddy;I. Pomeranz;S. Kajihara
我们提出了一种有效的方法，可以选择扫描设计中的最小可测试路径集，以便电路中的每一行都被包含它的最长可测试路径之一覆盖（如果有的话）。提出的路径选择方法基于逐步路径扩展过程，该过程使用延迟信息和关于不可测试路径的紧凑信息，以选择最长的路径，同时避免无法测试的路径。称为延迟分析和延迟约束路径扩展的技术用于加速测试路径的选择。与较早的方法相比，提出的方法很快，可以保证找到可测试的路径。此外，该过程还得出了所选路径的测试。提出了ISCAS89基准回路的实验结果，并提出了宽边测试，以证明该方法的有效性。
We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.