A 3 μW CMOS true random number generator with adaptive floating-gate offset cancellation
A 3 μW CMOS true random number generator with adaptive floating-gate offset cancellation
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DOI：
10.1109/jssc.2008.920327
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发表时间：
2008-05-01
影响因子：
5.4
通讯作者：
Diorio, Chris
中科院分区：
文献类型：
--
作者：
Holleman, Jeremy;Bridges, Seth;Diorio, Chris
提出了两种基于锁存亚稳的硬件随机数发生器。我们设计了第一个，直流零化RNG，用于极低功耗的操作。第二种是基于fir的RNG，它使用预测白化滤波器从生成的位序列中去除非随机成分。在这两种设计中，使用浮栅存储单元使我们能够预测和补偿直流偏移和其他非随机影响，同时最大限度地降低功耗。我们还提出了一种有效的数字后处理技术来改善随机性。我们在标准的0.35 μ m CMOS工艺中制造了两个rng。dc归零RNG被占用。模具面积为0.31 mm(2)，而基于fir的RNG占1.49 mm(2)。
This paper presents two novel hardware random number generators (RNGs) based on latch metastability. We designed the first, the DC-nulling RNG, for extremely low power operation. The second, the FIR-based RNG, uses a predictive whitening filter to remove nonrandom components from the generated bit sequence. In both designs, the use of floating-gate memory cells allows us to predict and compensate for DC offsets and other nonrandom influences while minimizing power consumption. We also present an efficient digital post-processing technique for improving randomness. We fabricated both RNGs in a standard 0.35 mu m CMOS process. The DC-nulling RNG occupied .031 mm(2) of die area, while the FIR-based RNG occupied 1.49 mm(2).