Multi retention level STT-RAM cache designs with a dynamic refresh scheme
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
复制标题
DOI：
10.1145/2155620.2155659
复制
发表时间：
2011-12
期刊：
影响因子：
--
通讯作者：
Zhenyu Sun;Xiuyuan Bi;Hai Helen Li;W. Wong;Zhong-Liang Ong;Xiaochun Zhu;Wenqing Wu
中科院分区：
文献类型：
--
作者：
Zhenyu Sun;Xiuyuan Bi;Hai Helen Li;W. Wong;Zhong-Liang Ong;Xiaochun Zhu;Wenqing Wu
自旋转移扭矩随机访问记忆（STT-RAM）由于其吸引人的特征而受到越来越多的关注：良好的可扩展性，零备用功率，非挥发性和辐射硬度。提出的缓存是通过技术缩小的降低泄漏功率的。具有相同的脚印的较大的缓存，通过减少缓存的整体性能。尤其是使用STT-RAM的水平缓存设计。隧道连接（MTJ）的设计。用于减少数据保留时间的快速STT-RAM位，提出了反控制的动态刷新方案，以维持数据的有效性。在先前的工作中提出的L1缓存。与使用传统的SRAM相比，总能量具有相对较大的缓存能力，我们提出了一个数据迁移方案，该方案将数据移动具有不同保留特性的缓存之间的数据实验表明，与以前的工作相比，我们提议的多保留水平STT-RAM CACHE平均减少了总能量的30％至70％，同时改善了IPC 2级和3级高速缓存层次结构的性能。
Spin-transfer torque random access memory (STT-RAM) has received increasing attention because of its attractive features: good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/9 ∼ 1/3 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses. However, deploying STT-RAM technology in L1 caches is challenging because of the long and power-consuming write operations. In this paper, we propose both L1 and lower level cache designs that use STT-RAM. In particular, our designs use STTRAM cells with various data retention time and write performances, made possible by different magnetic tunneling junction (MTJ) designs. For the fast STT-RAM bits with reduced data retention time, a counter controlled dynamic refresh scheme is proposed to maintain the data validity. Our dynamic scheme saves more than 80% refresh energy compared to the simple refresh scheme proposed in previous works. A L1 cache built with ultra low retention STTRAM coupled with our proposed dynamic refresh scheme can achieve 9.2% in performance improvement, and saves up to 30% of the total energy when compared to one that uses traditional SRAM. For lower level caches with relative large cache capacity, we propose a data migration scheme that moves data between portions of the cache with different retention characteristics so as to maximize the performance and power benefits. Our experiments show that on the average, our proposed multi retention level STT-RAM cache reduces 30 ∼ 70% of the total energy compared to previous works, while improving IPC performance for both 2-level and 3-level cache hierarchy.