Low-Power High-Speed Hybrid Temperature Heterogeneous Technology Digital Data Link
Low-Power High-Speed Hybrid Temperature Heterogeneous Technology Digital Data Link
复制标题
低功耗高速混合温度异构技术数字数据链路
DOI：
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复制
发表时间：
2013
影响因子：
1.8
通讯作者：
M. G. Sadrabadi
中科院分区：
文献类型：
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作者：
D. Gupta;J. Bardin;A. Inamdar;A. Dayalu;S. Sarwana;P. Ravindran;S. Chang;A. H. Coskun;M. G. Sadrabadi
由于单通量量子逻辑的能量/比特比标准室温逻辑低许多（六）个数量级，因此从4-K超导体电子器件到室温的高速数字数据链路具有挑战性。我们的方法，建立一个节能的高速数据链涉及到一个联合的电热设计的温度分布架构，使用不同的电子技术。这种差分数字数据链的设计涉及超导体，多个低温半导体和附加的室温半导体电路。目前的设计涉及三个低温半导体集成电路与多级低温冷却数字系统的集成。第一个低温半导体IC设计为在4 K下工作，功耗为0.3 mW，并直接与超导差分单通量量子/直流驱动器接口。为了测试它，超导载体芯片包含一个模数转换器已被设计用于HYPRES双（4.5和20）制造工艺。
High-speed digital data links from 4-K superconductor electronics to room temperature are challenging due to the fact that energy/bit for single flux quantum logic is many (six) orders of magnitude lower than that of standard room-temperature logic. Our approach of building an energy-efficient high-speed data link involves a joint electrical-thermal design of a temperature-distributed architecture using different electronic technologies. This differential digital data link design involves superconductor, multiple cryogenic semiconductor and additional room-temperature semiconductor circuitry. The current design involves three cryogenic semiconductor ICs for integration with a multistage cryocooled digital system. The first cryogenic semiconductor IC is designed to operate at 4 K with a power consumption of 0.3 mW and interface directly with the superconductor differential single flux quantum/dc drivers. For testing it, a superconductor carrier chip containing an analog-to-digital converter has been designed for the HYPRES dual- (4.5 and 20 ) fabrication process.