Instruction-level DfT for testing processor and IP cores in system-on-a-chip
Instruction-level DfT for testing processor and IP cores in system-on-a-chip
复制标题
用于测试片上系统中的处理器和 IP 核的指令级 DfT
DOI：
10.1109/dac.2001.156108
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
K. Cheng
中科院分区：
文献类型：
--
作者：
Wei;K. Cheng
通过使用可编程核运行测试程序来自测试片上系统（SOC）中的制造缺陷具有若干潜在益处，包括高速测试、由于消除专用测试电路而导致的低DfT开销以及测试期间的更好的功率和热管理。然而，这样的自测试策略可能需要冗长的测试程序并且可能无法实现足够高的故障覆盖率。我们提出了一种DfT的方法，以提高故障覆盖率，减少测试程序的长度，通过添加测试指令的片上可编程的核心，如微处理器的核心。本文讨论了一种有效的测试指令识别方法，可以导致最高的效益与低面积/性能开销。实验结果表明，与不使用测试级DfT的情况相比，通过增加测试指令，可以实现对可测路径延迟故障的完全故障覆盖，程序大小和运行时间减少20%以上.
Self-testing manufacturing defects in a system-on-a-chip (SOC) by running test programs using a programmable core has several potential benefits including, at-speed testing, low DfT overhead due to elimination of dedicated test circuitry and better power and thermal management during testing, However, such a self-test strategy might require a lengthy test program and might not achieve a high enough fault coverage. We propose a DfT methodology to improve the fault coverage and reduce the test program length, by adding test instructions to an on-chip programmable core such as a microprocessor core. This paper discusses a method of identifying effective test instructions which could result in highest benefits with low area/performance overhead. The experimental results show that with the added test instructions, a complete fault coverage for testable path delay faults can be achieved with a greater than 20% reduction in the program size and the program runtime, as compared to the case without instruction-level DfT.