i/sub DDT/ test methodologies for very deep sub-micron CMOS circuits
i/sub DDT/ test methodologies for very deep sub-micron CMOS circuits
复制标题
适用于超深亚微米 CMOS 电路的 i/sub DDT/ 测试方法
DOI：
10.1109/delta.2002.994659
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
David Wu
中科院分区：
文献类型：
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作者：
A. Chehab;R. Makki;M. Spica;David Wu
本文研究了三种基于i/sub DDT/-的测试方法，即双阈值i/sub DDT/、增量i/sub DDT/和延迟i/sub DDT/，并比较了它们在检测甚深亚微米随机逻辑电路缺陷中的有效性。目标缺陷是电阻性开路和电阻性桥接。我们提出了49个缺陷的初步模拟结果，研究三种测试方法中的每一种的缺陷灵敏度。本文报告了我们的初步结果，这三种测试方法使用一个相对较小的晶体管级的样本电路，并不意味着在生产环境中的任何可行性。本文所述的测试方法是本发明公开的主题。
In this paper, we investigate three i/sub DDT/-based test methodologies, Double Threshold i/sub DDT/, Delta i/sub DDT/, and Delayed i/sub DDT/, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the three test methods. This paper reports our preliminary results on these three test methods using a relatively small transistor-level sample circuit, and is not intended to imply any feasibility in a production environment. The test methods presented herein are the subject of a current invention disclosure.