Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture
Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture
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适用于低功耗细粒度可重构 VLSI 架构的电流源共享差分对电路
DOI：
10.1109/ismvl.2012.13
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
Xu Bai and Michitaka Kameyama
中科院分区：
文献类型：
--
作者：
Yuusuke Yamaguchi;Yoshinori Tatematsu;Teruo Saito;Ryosuke Ikeda;Jagadish C Mudiganti;Isamu Ogawa and Toshitaka Idehara;Xu Bai and Michitaka Kameyama
提出了一种使用多值开关块和二进制逻辑模块的位串行可重构VLSI。在小区中，利用多值信令来实现紧凑的开关块。介绍了一种二进制控制电流导引技术，利用可编程串联门控差分对电路实现高性能低功耗算术逻辑运算，如任意双变量二进制逻辑运算和全加器求和。此外，电流源共享之间的串联选通差分对电路和电流模式D锁存器的建议，以减少电流源的数量，以降低功耗。其结果是，所提出的位串行单元的功耗和延迟时间分别减少到63%和72%，与以前的多值位串行单元相比。
A bit-serial reconfigurable VLSI using multiple-valued switch blocks and binary logic modules is proposed. In a cell, multiple-valued signaling is utilized to implement a compact switch block. Binary-controlled current steering technique is introduced utilizing a programmable series-gating differential-pair circuit to implement high-performance low-power arithmetic logic operations such as an arbitrary two-variable binary logic operation and a full-adder sum. Moreover, current-source sharing between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count to reduce power consumption. As a result, the power consumption and the delay time of the proposed bit-serial cell are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued bit-serial cell.