A 2.6 GB/s multi-purpose chip-to-chip interface
A 2.6 GB/s multi-purpose chip-to-chip interface
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2.6 GB/s 多用途芯片间接口
DOI：
10.1109/isscc.1998.672417
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发表时间：
1998
期刊：
影响因子：
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通讯作者：
R. Crisp
中科院分区：
文献类型：
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作者：
B. Lau;Yiu;A. Moncayo;J. Ho;M. Allen;J. Salmon;J. Liu;M. Muthal;C. Lee;T. Nguyen;B. Horine;M. Leddige;K. Huang;J. Wei;L. Yu;R. Tarver;Y. Hsia;R. Vu;E. Tsern;H. Liaw;J. Hudson;D. Nguyen;K. Donnelly;R. Crisp
高速接口单元在一个由双字节数据字段和一个字节命令字段组成的26b宽I/O接口上提供800mb /s/pin数据传输速率。对于2.6 GB/s的数据速率，400mhz时钟恢复电路保证在I/O接口的两个时钟边传输800mv摆幅数据的时间裕度。来自高速接口的数据在内部反序列化，以提供100 MHz (f/4) ASIC时钟接口。测试芯片包含三个超大单元和内置时钟同步电路，以确保三个超大单元之间正确的数据传输，对延迟的影响最小。控制阻抗总线，称为通道，具有精心的PCB布局，确保板上800 Mb/s/引脚数据速率，用于asic到asic或asic到dram系统配置。
A high-speed interface cell delivers 800 Mb/s/pin data transfer rate on a 26b wide I/O interface consisting of a dual-byte data field and a byte-wide command field. For 2.6 GB/s data rate, a 400 MHz clock recovery circuit guarantees the timing margin for transferring 800 mV swing data at both clock edges over the I/O interface. Data from the high speed interface is internally deserialized to provide a 100 MHz (f/4) ASIC clock interface. A test chip contains three megacells and built-in clock synchronization circuits to ensure proper data transfer between the three megacells with minimal impact on latency. Controlled impedance buses, referred to as channels, with careful PCB layout ensure 800 Mb/s/pin data rate on-board for ASIC-to-ASIC or ASIC-to-DRAM system configuration.