A retargetable framework for instruction-set architecture simulation
A retargetable framework for instruction-set architecture simulation
复制标题
用于指令集架构模拟的可重定向框架
DOI：
10.1145/1151074.1151083
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
P. Mishra
中科院分区：
文献类型：
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作者：
Mehrdad Reshadi;N. Dutt;P. Mishra
指令集架构 (ISA) 模拟器是当今处理器和软件设计过程中不可或缺的一部分。虽然架构的复杂性不断增加，需要高性能仿真，但可用架构的多样性不断增加，使得可重定向性成为指令集仿真器的关键功能。可重定位性需要通用模型，而高性能则需要针对特定的定制。为了解决这些相互矛盾的要求，我们开发了通用指令模型和通用解码算法，有助于 ISA 模拟器轻松高效地重新定位各种处理器架构，例如 RISC、CISC、VLIW 和可变长度指令集处理器。指令模型用于生成与架构手册非常相似的紧凑且易于调试的指令描述。这些描述用于生成高性能模拟器。我们的可重定向框架结合了解释模拟的灵活性和编译模拟的速度。模拟器的生成与模拟引擎完全分开。因此，我们可以将任何快速模拟技术合并到我们的可重定向框架中，而不会引入任何性能损失。为了证明这一点，我们在可重定向框架中融入了快速 IS-CS 模拟引擎，与此类中最知名的模拟器相比，该引擎的性能提高了 70%。我们使用两种流行但不同的现实架构（SPARC 和 ARM）来说明我们方法的可重定位性。
Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high-performance simulation, the increasing variety of available architectures makes retargetability a critical feature of an instruction-set simulator. Retargetability requires generic models while high-performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability of the ISA-simulator for a wide range of processor architectures, such as RISC, CISC, VLIW, and variable length instruction-set processors. The instruction model is used to generate compact and easy to debug instruction descriptions that are very similar to that of architecture manual. These descriptions are used to generate high-performance simulators. Our retargetable framework combines the flexibility of interpretive simulation with the speed of compiled simulation. The generation of the simulator is completely separate from the simulation engine. Hence, we can incorporate any fast simulation technique in our retargetable framework without introducing any performance penalty. To demonstrate this, we have incorporated fast IS-CS simulation engine in our retargetable framework which has generated 70% performance improvement over the best known simulators in this category. We illustrate the retargetability of our approach using two popular, yet different, realistic architectures: the SPARC and the ARM.