Energy-efficient STDP-based learning circuits with memristor synapses
Energy-efficient STDP-based learning circuits with memristor synapses
复制标题
具有忆阻器突触的基于 STDP 的节能学习电路
DOI：
10.1117/12.2053359
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发表时间：
2014
影响因子：
4
通讯作者：
K. Campbell
中科院分区：
文献类型：
--
作者：
Xinyu Wu;V. Saxena;K. Campbell
传统的冯诺依曼架构，处理器和存储器分离，不适合处理哺乳动物大脑可以有效处理的并行数据流。此外，研究人员现在设想的计算架构可以通过实时识别时空关系和解决复杂的模式识别问题来实现对大量数据的认知处理。与标准CMOS技术集成的忆阻器交叉点阵列有望实现大规模并行和低功耗的神经形态计算架构。近年来，在模拟大脑皮层数据处理的脉冲神经网络（SNN）方面取得了重大进展。这些结构由密集的神经元网络和在轴突和树突之间形成的突触组成。此外，正在研究无监督或有监督的竞争性学习方案，以进行网络的全球训练。与软件实现相比，这些网络的硬件实现需要大量的电路开销来寻址和单独更新网络权重。相反，我们采用生物启发的学习规则，如spike- time -dependent plasticity （STDP）来有效地更新网络的局部权重。为了在芯片上实现snn，我们建议在CMOS芯片的后端（BEOL）中使用密集集成的混合信号集成和火神经元（ifn）和忆阻器的交叉点阵列。新的IFN电路被设计用于驱动记忆突触并行，同时保持整体功率效率（<1 pJ/spike/synapse），即使在峰值速率大于10 MHz时也是如此。我们介绍了带有忆阻器突触的IFN的电路设计细节和仿真结果，以及它对输入尖峰序列的响应和STDP学习特性。
It is now accepted that the traditional von Neumann architecture, with processor and memory separation, is ill suited to process parallel data streams which a mammalian brain can efficiently handle. Moreover, researchers now envision computing architectures which enable cognitive processing of massive amounts of data by identifying spatio-temporal relationships in real-time and solving complex pattern recognition problems. Memristor cross-point arrays, integrated with standard CMOS technology, are expected to result in massively parallel and low-power Neuromorphic computing architectures. Recently, significant progress has been made in spiking neural networks (SNN) which emulate data processing in the cortical brain. These architectures comprise of a dense network of neurons and the synapses formed between the axons and dendrites. Further, unsupervised or supervised competitive learning schemes are being investigated for global training of the network. In contrast to a software implementation, hardware realization of these networks requires massive circuit overhead for addressing and individually updating network weights. Instead, we employ bio-inspired learning rules such as the spike-timing-dependent plasticity (STDP) to efficiently update the network weights locally. To realize SNNs on a chip, we propose to use densely integrating mixed-signal integrate-andfire neurons (IFNs) and cross-point arrays of memristors in back-end-of-the-line (BEOL) of CMOS chips. Novel IFN circuits have been designed to drive memristive synapses in parallel while maintaining overall power efficiency (<1 pJ/spike/synapse), even at spike rate greater than 10 MHz. We present circuit design details and simulation results of the IFN with memristor synapses, its response to incoming spike trains and STDP learning characterization.