Secure Function Evaluation Using an FPGA Overlay Architecture
Secure Function Evaluation Using an FPGA Overlay Architecture
复制标题
使用 FPGA 叠加架构进行安全功能评估
DOI：
10.1145/3020078.3021746
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
M. Leeser
中科院分区：
文献类型：
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作者：
Xin Fang;Stratis Ioannidis;M. Leeser
由于互联网上的大量个人数据的收集和挖掘，安全功能评估(SFE)近年来受到了相当大的关注，但巨大的计算成本仍然使其不切实际。在本白皮书中，我们利用硬件加速来解决SFE固有的可扩展性和效率挑战。为此，我们提出了一种通用的、可重构的SFE实现，作为粗粒度的FPGA覆盖体系结构。与与特定SFE结构的执行捆绑在一起的定制方法相反，我们的设计允许重新调整FPGA的用途以评估不同的SFE任务，而不需要重新编程。我们的实现表明，与评估乱码电路的软件包相比，改进了几个数量级，并证明了被评估的电路可以在几乎没有开销的情况下进行更改。
Secure Function Evaluation (SFE) has received considerable attention recently due to the massive collection and mining of personal data over the Internet, but large computational costs still render it impractical. In this paper, we leverage hardware acceleration to tackle the scalability and efficiency challenges inherent in SFE. To that end, we propose a generic, reconfigurable implementation of SFE as a coarse-grained FPGA overlay architecture. Contrary to tailored approaches that are tied to the execution of a specific SFE structure, and require full reprogramming of an FPGA with each new execution, our design allows repurposing an FPGA to evaluate different SFE tasks without the need for reprogramming. Our implementation shows orders of magnitude improvement over a software package for evaluating garbled circuits, and demonstrates that the circuit being evaluated can change with almost no overhead.