Dataflow object detection system for FPGA-based smart camera
Dataflow object detection system for FPGA-based smart camera
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DOI：
10.1049/iet-cds.2015.0071
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发表时间：
2016-07-01
影响因子：
1.3
通讯作者：
Berry, Francois
中科院分区：
文献类型：
--
作者：
Bourrasset, Cedric;Maggiani, Luca;Berry, Francois
基于嵌入式计算机视觉的智能系统在许多研究领域都提出了具有挑战性的问题，包括实时视觉处理、通信协议或分布式算法。使用高分辨率图像传感器的相机产生的数据量要求以数字视频帧速率处理强大的计算系统。因此，设计高效、灵活、具有车载处理能力的智能摄像机已成为依赖于图像传感器节点级别的分散处理的智能视觉系统扩展的关键问题。在这种背景下，与基于通用处理器的平台相比，基于现场可编程门阵列(现场可编程门阵列)的平台支持海量数据并行，提供了匹配实时处理限制的巨大机会。在这项研究中，作者描述了一个可配置的目标检测应用程序在这样一个平台上的实现，该应用程序根据计算的数据流模型进行了重新定义。该应用依赖于方向梯度直方图的计算和基于线性支持向量机的分类。它使用CAPH编程语言进行描述，允许从高级数据流规范自动生成有效的硬件描述，而无需预先了解硬件描述语言，如VHDL语言或Verilog。结果表明，与手写的HDL码相比，生成的代码的性能不会受到显著的开销影响。
Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.