Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
复制标题
DOI：
10.1109/tadvp.2009.2021661
复制
发表时间：
2009-11-01
影响因子：
--
通讯作者：
Chai, T. C.
中科院分区：
文献类型：
--
作者：
Selvanayagam, Cheryl S.;Lau, John H.;Chai, T. C.
大多数 TSV 都填充有铜；硅多晶和钨是替代品。铜的热膨胀系数（CTE）（约17.5 x 10(-6)/摄氏度）比硅的热膨胀系数（约2.5 x 10(-6)/摄氏度）高几倍。因此，当铜填充硅通孔（TSV）受到温度负载时，铜和硅/电介质（例如SiO2）之间存在非常大的局部热膨胀失配，这将在铜和硅之间以及铜和电介质之间的界面处产生非常大的应力和应变。这些应力/应变可能足够高以在界面之间引入分层。在本文中，已经确定了各种纵横比（硅厚度和 TSV 直径）下铜、硅和电介质之间界面处的非线性热应力和应变。 TSV 的主要应用之一是作为中介层。由于摩尔定律（缩放/积分），硅芯片变得越来越大，引脚排列越来越高，并且间距越来越细。因此，传统的基板，例如BT（双马来酰亚胺三嗪）不再能够支持这些类型的硅芯片，并且需要硅中介层（基板）来通过硅基板上的硅通孔将芯片上的极细间距和高引脚数焊盘重新分布到更大的间距和更少的引脚数。根据填充铜的 TSV 的通孔尺寸和间距，填充铜的 TSV 中介层的有效 CTE 可能高达 10 x 10(-6)/摄氏度。因此，硅芯片和填充铜的 TSV 基板之间的整体热膨胀失配可能非常大，并且它们之间的凸块（通常非常小，例如微凸块）可能无法在热条件下生存。在本研究中，针对各种通孔尺寸和间距以及各种温度条件，确定了硅芯片和铜填充 TSV 中介层（有或没有底部填充）之间的微凸块中的非线性应力和应变。这些结果对于以下方面很有用：1) 决定是否需要底部填充来保证微凸块的可靠性；2) 选择底部填充材料以最大限度地减少微凸块中的应力和应变。
Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (similar to 17.5 x 10(-6)/degrees C) is a few times higher than that of silicon (similar to 2.5 x 10(-6)/degrees C). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 x 10(-6)/degrees C. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps.