Charge-Trap Transistors for CMOS-Only Analog Memory
Charge-Trap Transistors for CMOS-Only Analog Memory
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DOI：
10.1109/ted.2019.2933484
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发表时间：
2019-10-01
影响因子：
3.1
通讯作者：
Iyer, Subramanian S.
中科院分区：
文献类型：
--
作者：
Gu, Xuefeng;Wan, Zhe;Iyer, Subramanian S.
自从我们使用CMOS纯电荷陷阱晶体管（CTT）作为模拟突触来演示无监督学习以来，人们对利用该设备进行各种其他神经网络（NN）应用的兴趣越来越大。然而，大多数这些研究仅限于模拟由于缺乏详细的实验设备表征。在这篇文章中，我们提供了一个全面的调查CTT的编程行为，包括模拟保留，内部和设备间的变化，以及微调的设备，无论是单个设备和设备在一个集成阵列。研究发现，编程后，沟道电流逐渐增加到一个较高的水平，当器件被编程到一个较高的阈值电压时，漂移较大。通过适当地考虑这种后编程电流增加，可以将各个器件编程为五位的等效精度，并且可以为阵列中的器件实现三位。我们的研究结果揭示了使用CTT作为CMOS模拟存储器设备的前景。
Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra-and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device.