8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package
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8.1 Lakefield 和移动计算:采用 12×12mm2、1mm 层叠封装的 3D 堆叠 10nm 和 22FFL 混合处理器系统
DOI:
10.1109/isscc19947.2020.9062957
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发表时间:
2020
期刊:
影响因子:
--
通讯作者:
R. Kumar
中科院分区:
文献类型:
--
作者:
Wilfred Gomes;Sanjeev Khushu;D. Ingerly;P. Stover;Nasirul Chowdhury;F. O’Mahony;A. Balankutty;Noam Dolev;Martin G. Dixon;Lei Jiang;Surya Prekke;B. Patra;P. Rott;R. Kumar
The Lakefield processor combines heterogeneous 3D die stacking also called Foveros, with hybrid computing to enable a new class of small form factor mobile products. The stacked die and implementation of the 3D package with PoP memory is shown in Fig. 8.1.1. The compute die is on Intel 10nm+ for power-performance and includes the CPU, GPU, IPU, memory and display engine based on IP from the Icelake product family. It includes one Core™ and four Atom™ cores in a hybrid configuration connected using a cache-coherent fabric. Both core types are exposed to the operating system which selects the best core depending on the performance and power characteristics of the workload. The memory subsystem supports LPDDR4X PoP in a 4×16 configuration. The base die is on Intel 22FFL and contains the chipset functionality including PCIe Gen3, USB type-C, storage, audio and a sensor hub. Combining 10nm and 22FFL in 3D enables a large dynamic range of performance and power modes. The 3D dies communicate with a low-power inter-die I/O called the Foveros Die Interface (FDI). The power delivery has been optimized to leverage a PMIC-based power delivery compared to previous to reach the low power and small form factors.