A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching
A Fast Wire-Routing Method and an Automatic Layout Tool for RSFQ Digital Circuits Considering Wire-Length Matching
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DOI：
10.1109/tasc.2018.2793203
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发表时间：
2018-01
影响因子：
1.8
通讯作者：
Nobutaka Kito;K. Takagi;N. Takagi
中科院分区：
文献类型：
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作者：
Nobutaka Kito;K. Takagi;N. Takagi
提出了一种考虑线长匹配的无源传输线快速布线方法。该方法处理相邻列有源器件之间的沟道布线问题，并基于模拟退火算法生成紧凑区域内具有指定附加长度的PTL路径。它使用一种从符号序列中生成路径的方法来有效地搜索解决方案。还示出了自动布局工具。它由一个放置器和路由器的基础上提出的方法。布局器使用PTL的总延伸长度进行长度匹配，作为使用模拟退火的详细布局的评估指标之一。通过引入该度量，减少了布线阶段的总扩展长度，获得了紧凑的布局。使用该工具，可以建立从HDL描述到版图生成的设计流程。作为实验结果，示出了由该工具设计的加法器布局。
A fast wire-routing method considering wire-length matching of passive transmission lines (PTLs) is proposed. The method deals with channel routing between adjacent columns of active devices, and generates paths of PTLs with specified additional length packed in compact area based on simulated annealing. It uses a generation method of paths from a sequence of symbols for searching solutions efficiently. An automatic layout tool is also shown. It consists of a placer and a router based on the proposed method. The placer uses total extension length of PTLs for length matching as one of the evaluation metrics for detailed placement using simulated annealing. By introducing this metric, total extension length in routing phase is reduced and compact layouts are obtained. Using the tool, design flow from HDL descriptions to layout generation can be established. As an experimental result, a layout of an adder designed by the tool is shown.