Automated I/O Library Generation for Interposer-Based System-in-Package Integration of Multiple Heterogeneous Dies
Automated I/O Library Generation for Interposer-Based System-in-Package Integration of Multiple Heterogeneous Dies
复制标题
自动生成 I/O 库，用于多个异构芯片的基于内插器的系统级封装集成
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
S. Mukhopadhyay
中科院分区：
文献类型：
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作者：
Minah Lee;Ashutosh Kumar Singh;H. Torun;Jinwoo Kim;S. Lim;M. Swaminathan;S. Mukhopadhyay
在单个封装中集成多个芯片的系统级封装(Sip)可以实现比集成电路(IC)的板上集成高得多的性能，同时与大型片上系统(SoC)相比降低设计成本/工作量。然而，在具有许多芯片的SiPS的设计中的一个主要挑战是自动设计和插入输入/输出(I/O)单元，以最小化线迹的能量和延迟。本文提出了一种用于全数字I/O电路的自动单元库生成流程。在给定SIP线迹线的参数化模型的情况下，我们的方法自动设计、优化和生成I/O单元的布局，以使延迟/能量最小化。在基于插入器的sip集成上，考虑了28 nm的cmos工艺和65 nm的BEOL工艺，给出了所提出的流程。给出多芯片sip设计和相关的插入线走线，本文演示了自动I/O库单元生成可以减少芯片到芯片的最大通信延迟或能量。我们针对不同的插入器参数和sip设计演示了所提出的流程，以显示芯片-插入器协同设计的可行性。
System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign.