A Twisted Bit Line Technique for Multi-Mb Drams
A Twisted Bit Line Technique for Multi-Mb Drams
复制标题
多兆位随机存储器的扭曲位线技术
DOI：
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发表时间：
1988
期刊：
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通讯作者：
K. Fujishima
中科院分区：
文献类型：
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作者：
T. Yoshihara;H. Hidaka;Y. Matsuda;K. Fujishima
随着DRAM的集成密度的增长，在按比例缩放的存储单元阵列中固有的新型存储器阵列噪声已经成为不可避免的问题：由于位线-位线耦合电容而引起的位线间耦合噪声，随着位线间距变小而增加，以及由于存储器的传输栅极晶体管的镜像电容而引起的击穿反馈噪声，它们在高密度DRAM中成为严重的问题。通过缩小晶体管的垂直尺寸可以部分地解决晶体管间耦合噪声问题，但是这受到诸如电迁移和由于晶体管电阻的增加而导致的性能下降的问题的限制。本文将提出和演示的DRAM架构，以消除噪声，并克服未来DRAM的缩放问题。传统折叠位线设计中的两种内部耦合噪声如图1所示。它们是对间耦合N1（取决于数据模式）和对内耦合N2。通过模拟256 K 16 Mb级PMOS结构估算的总PMOS电容CB和PMOS间耦合电容CBB如图2所示。图3显示了最差情况下的信号幅度与跨导电容的关系，模拟结果与具有实际跨导结构和工作条件的测试器件上的测量结果非常一致。根据这些结果，尽管使用了薄的多hitline，但由于16 Mb的跨导耦合噪声结构而导致的信号降低估计为总信号幅度的40%。图4显示了所提出的双绞线（TBL）技术，该技术消除了内部耦合噪声并改善了信号。TBL配置中的对间耦合噪声被均等地耦合到相邻的成对位线，并且在差分感测操作中被消除。在改进的TBL情况下，对内耦合噪声也被消除，信号的改善程度是TBL情况下的两倍，如图5所示。因此，在修改的TBL中，位线-位线耦合电容不会引起耦合噪声，而只是增加了CB。图6显示了仅按比例缩小A1位线间距和宽度时估计的最差情况信号。TBL和修改的TBL配置分别允许0.7和0.45的因子的恒定垂直尺寸缩放（其仅对应于一代和两代DRAM），同时保持与lhlb级折叠位线配置相同的信号损耗水平。
16M 4M 1M AS THE INTEGRATION DENSITY OF THE DRAM has grown, new types of memory array noise inherent in the scaled memory cell array have emerged as inevitable problems: inter-bitline coupling noise due to the bitline-bitline coupling capacitance, increased as the bitline pitch becomes smaller, and hitlinewordline feedback noise due t o mirror capacitance of the transfer-gate transistors of the memory They become serious problems in high density DRAMs. The inter-bitline coupling noise problem may be partially solved by scaling down the vertical dimension of the bitline, but this is limited by problems such as the electro-migration and the performance degradation due to the increase o f the bitline resistance. This paper will propose and demonstrate bitline architecture to eliminate the noise and also overcome the scaling problem of future DRAMs. Two kinds of inter-bitline coupling noise in conventional folded bit-line design are illustrated in Figure 1. They are inter-pair coupling N1 (which is dependent on the data pattern) and intra-pair coupling N2. The total bitline capacitance CB and the inter-bitline coupling capacitance CBB estimated by simulation of the 256K 16Mb level bitline structures are shown in Figure 2. Figure 3 shows the worst-case-signal amplitude versus inter-bitline capacitance, which simulated is in good agreement with measurement on a test device that has the actual bitline structures and operating conditions. From these results, the signal reduction due t o the inter-bitline coupling noise 16Mb bitline structure is estimated to be 40% of the total signal amplitude, in spite of the use of a thin poly-hitline. Figure 4 shows proposed Twisted Bit Line (TBL) techniques which cancel the inter-bitline coupling noise and improve the signal. The inter-pair coupling noise in the TBL configurations is equally coupled to adjacent paired bitlines and cancelled in the differential sensing operation. In the modified TBL case, the intra-pair coupling noise is also eliminated and the signal is improved twice as much as in the TBL case, as shown in Figure 5. Thus in the modified TBL, the bitline-bitline coupling capacitance does not cause coupling noise, but only increases the CB. Figure 6 shows the worst-case signal estimated with only the spacing and width of the A1 bit line proportionally scaled down. The TBL and modified TBL configurations permit the constantvertical-dimension scaling by factors of 0.7 and 0.45, respectively, (which correspond to just one and two DRAM generations), while maintaining the same level of signal loss as the lhlb level folded bit-line configuration.