Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network
Multiple-valued logic-in-memory VLSI based on a floating-gate-MOS pass-transistor network
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DOI：
10.1109/isscc.1998.672432
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发表时间：
1998-02
期刊：
影响因子：
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通讯作者：
T. Hanyu;K. Teranishi;M. Kameyama
中科院分区：
文献类型：
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作者：
T. Hanyu;K. Teranishi;M. Kameyama
存储器中的逻辑结构是一种解决存储器和逻辑模块之间通信瓶颈的方法，它将存储功能分布在一个逻辑电路平面上，这是当前深亚微米超大规模集成电路系统技术中最严重的问题之一。这种基于浮栅MOS晶体管的逻辑存储器VLSI将存储和开关功能合并在多值输入和二进制输出的组合逻辑电路中，这对于实现并行算术和逻辑电路是有用的。本文提出了一种四值输入二值输出组合逻辑电路的一般结构。它有两种输入，外部和存储常数输入。在存储器中逻辑VLSI中，大量存储的数据不仅以字并行的方式分布，而且以数字并行的方式分布。
A logic-in-memory structure, in which storage functions are distributed over a logic-circuit plane, is a solution to the communication bottleneck between memory and logic modules, one of the most serious problems in recent deep submicron VLSI systems technology. This logic-in-memory VLSI based on floating-gate MOS transistors merges storage and switching functions in a multiple-valued-input and binary-output combinational logic circuit that is useful for the realization of parallel arithmetic and logic circuits. The paper presents a general structure of a 4-valued-input and binary-output combinational logic circuit. It has two kinds of inputs, external and stored constant inputs. In the logic-in-memory VLSI, a large number of stored data are distributed in not only word-parallel but also in digit parallel manners.