On-chip protection for automotive integrated circuits robustness
On-chip protection for automotive integrated circuits robustness
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DOI：
10.1109/iccdcs.2012.6188920
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发表时间：
2012-03
期刊：
影响因子：
--
通讯作者：
J. Salcedo;D. Clarke;J. Hajjar
中科院分区：
文献类型：
--
作者：
J. Salcedo;D. Clarke;J. Hajjar
On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second-level protection stage is customized to sustain the relatively lower IC-level ESD stress, and the third level protection stage absorbs the initial transient voltage impulse.
