System Verilog Assertions Synthesis Based Compiler
System Verilog Assertions Synthesis Based Compiler
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基于系统 Verilog 断言综合的编译器
DOI：
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发表时间：
2016
期刊：
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通讯作者：
Mohamed Abdelsalam
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文献类型：
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作者：
Omar Amin;Youssef Ramzy;Omar Ibrahem;A. Fouad;K. Mohamed;Mohamed Abdelsalam
提出了一种系统Verilog Assertions(SVA)综合编译器的体系结构，它将不可综合的系统Verilog断言转换成可综合的等价Verilog模块，以便将它们转换成数字硬件电路，用于观察运行设计的运行情况。提出的体系结构基于两个主要规则：“简单的编译器结构”和“泛型实现”。断言合成之所以是一个好主意，是因为可以使用这些合成的断言来定位错误(如果存在)，从而使调试过程变得更高效、更快，而且它还可以全面了解在FPGA上运行的设计，这使得基于设计原型的验证-特别是对于SoC-在识别错误方面更高效、更准确，并准确地告知系统故障发生的原因。此外，还可以使用断言硬件检查器来监视基于FPGA的关键应用程序的性能。因此，为了尽可能保持区域效益，资源利用是一个需要考虑的非常重要的方面。
This paper presents an architecture of system Verilog assertions (SVA) synthesis compiler, which translates the un-synthesizable System Verilog assertions, into synthesizable equivalent Verilog modules, in order to convert them to digital hardware circuits, used to watch how the running design performs. The proposed architecture is based on two main rules: "Simple compiler structure" and "generic implementation". The reason behind why assertions synthesis is a good idea, is that these synthesized assertions can be used in order to localize errors if they exist, so debugging process becomes more efficient, faster, and also, it gives a full visibility of the running design on FPGA, which makes design prototyping based verification – especially for SoCs – more efficient, accurate in recognizing bugs, and tell precisely, why system failures occur. Also, assertions hardware checkers can be used to keep eyes on the performance of critical FPGA-based applications. Therefore, resources utilization was a very important aspect to be considered in order to maintain area effectiveness as most as possible.