An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
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DOI：
10.1109/jssc.2022.3199241
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发表时间：
2022-12
影响因子：
5.4
通讯作者：
Tian Xie;Tzu-Han Wang;Zhe Liu;Shaolan Li
中科院分区：
文献类型：
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作者：
Tian Xie;Tzu-Han Wang;Zhe Liu;Shaolan Li
为了设计低过采样高分辨率噪声整形逐次逼近寄存器(NS-SAR)模数转换器(ADC)，需要解决两个主要瓶颈。一种是用简单、低功耗的硬件实现高阶优化NS，最大限度地保持SAR的高效性；另一种是减轻采样噪声和输入驱动负担。本文提出了一个四阶NS-SAR模数转换器，协同解决了这两个挑战。提出了一种新颖的误差反馈-级联谐振器前馈(EF-CRFF)结构和噪声抑制的环路缓冲(BIL)技术。前者综合了EF和CRFF两种结构的优点，在稳健性和能效之间取得了平衡，而后者则同时保证了ADC的低噪声和易于驱动。原型采用65nmCMOS工艺，在小功率比为5时，获得了84.1dB500 kHz带宽的信噪比(SNDR)。在1.2V电源(包括2V电源下的环路缓冲器)下的功耗为133.8美元，获得了180dBSchreier品质因数。
To design a low-oversampled high-resolution noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs), two main bottlenecks need to be addressed. One is to implement high-order optimized NS with simple and low-power hardware that maximally preserves a SAR’s efficient nature, and the other is to alleviate the sampling noise and input driving burden. This article presents a fourth-order NS-SAR ADC that synergistically addresses both challenges. It proposes an innovative error feedback-cascaded resonator feed-forward (EF-CRFF) structure and a noise-mitigated buffer-in-loop (BIL) technique. The former balances the robustness and energy efficiency by combining the merits of EF and CRFF structures, while the latter ensures the ADC to be low noise and easy-to-drive simultaneously. Prototyped in 65-nm CMOS technology, this work achieves 84.1-dB signal-to-noise-distortion ratio (SNDR) with 500-kHz bandwidth (BW) under a small OSR of 5. The prototype consumes 133.8- $\mu \text{W}$ power under 1.2-V supply (including the power of in-loop buffer under 2-V supply), leading to a 180-dB Schreier figure of merit (FoM).