An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard
An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard
复制标题
DOI：
10.1109/tcsii.2014.2362721
复制
发表时间：
2014-10
期刊：
影响因子：
--
通讯作者：
Yun Chen;Qichen Zhang;Di Wu;Changsheng Zhou;Xiaoyang Zeng
中科院分区：
文献类型：
--
作者：
Yun Chen;Qichen Zhang;Di Wu;Changsheng Zhou;Xiaoyang Zeng
提出了一种面积有效的多速率低密度奇偶校验卷积码（LDPC-CC）译码器。采用分层解码算法，解码器的性能优于消息传递算法，外部消息的存储由基于变量节点改为基于校验节点。然后，使用归一化最小和（NMS）算法，可以将外部消息约简为第一和第二最小绝对值、第一最小绝对值的位置索引、所有外部消息的符号以及所有符号的乘积。提出了一种基于存储器的专用集成电路结构的LDPC-CC解码器，支持这些方法的IEEE 1901标准。基于SMIC 130 nm互补金属氧化物半导体工艺，设计并实现了一个支持IEEE 1901中定义的所有LDPC码速率（1/2，2/3，3/4，4/5）的解码器。建议的解码器达到300 Mb/s的最大吞吐量在180 MHz的最大工作频率。核心面积为3.55 mm 2，有10个处理器。在4/5码率和180 MHz频率下，平均功耗为200.4 mW，功率效率为66.8 pJ/bit/proc. Very large scale integration结果表明，该译码器具有存储和面积效率。
An area-efficient multirate low-density parity-check convolutional code (LDPC-CC) decoder is presented in this brief. Using the layered decoding algorithm, the decoder achieves a better performance than the message-passing algorithm; the extrinsic-message storing is switched from variable node based to check node based. Then, using the normalized min-sum (NMS) algorithm, the extrinsic messages can be reduced to the first and second minimum absolute values, the position index of the first minimum absolute value, the signs of all extrinsic messages, and the product of all the signs. A memory-based application-specific integrated circuit architecture of the LDPC-CC decoder that supports these methods is proposed for the IEEE 1901 standard. Based on a SMIC 130-nm complementary metal-oxide-semiconductor process, a decoder that can support all the code rates of the LDPC-CCs defined in IEEE 1901 (1/2, 2/3, 3/4, 4/5) is fabricated and evaluated. The proposed decoder attains a maximum throughput of 300 Mb/s at a maximum operating frequency of 180 MHz. The core area is 3.55 mm2 with ten processors. The average power consumption is 200.4 mW at code rate 4/5 and a frequency of 180 MHz, and the power efficiency is 66.8 pJ/bit/proc. The very large scale integration results show that the decoder is both memory and area efficient.