Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
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DOI：
10.1109/jssc.2023.3313116
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发表时间：
2024-03
影响因子：
5.4
通讯作者：
Kathleen Feng;Taeyoung Kong;Kalhan Koul;J. Melchert;Alex Carsello;Qiaoyi Liu;Gedeon Nyengele;Maxwell Strange;Kecheng Zhang;Ankita Nayak;Jeff Setter;James J. Thomas;Kavya Sreedhar;Po-Han Chen;Nikhil Bhagdikar;Zachary Myers;Brandon D'Agostino;Pranil Joshi;Stephen Richardson;Christopher Torng;Mark Horowitz;Priyanka Raina
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文献类型：
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作者：
Kathleen Feng;Taeyoung Kong;Kalhan Koul;J. Melchert;Alex Carsello;Qiaoyi Liu;Gedeon Nyengele;Maxwell Strange;Kecheng Zhang;Ankita Nayak;Jeff Setter;James J. Thomas;Kavya Sreedhar;Po-Han Chen;Nikhil Bhagdikar;Zachary Myers;Brandon D'Agostino;Pranil Joshi;Stephen Richardson;Christopher Torng;Mark Horowitz;Priyanka Raina
Amber是一种芯片（SOC），具有粗粒的可重新配置阵列（CGRA），用于加速密集的线性代数应用程序，例如机器学习（ML），图像处理和计算机视觉。加速器 - 组合代码流动；编译器会自动更新硬件，从而可以对硬件 - 软件系统进行连续的应用程序级别的评估。琥珀色的特征：1）CGRA的动态部分重构（DPR），以通过在应用程序之间快速切换和在同时应用程序之间分配资源，以提供高效线性映射的流媒体访问模式； 3）低空超越和复杂的算术操作。有效布局的方法是其基于层的设计。 Amber分别具有高达3902美元的$ \ times $，152 $ \ times $，和107 $ \ times $更好的能量延迟产品（EDP）。
Amber is a system-on-chip (SoC) with a coarse-grained reconfigurable array (CGRA) for acceleration of dense linear algebra applications, such as machine learning (ML), image processing, and computer vision. It is designed using an agile accelerator–compiler codesign flow; the compiler updates automatically with hardware changes, enabling continuous application-level evaluation of the hardware–software system. To increase hardware utilization and minimize reconfigurability overhead, Amber features the following: 1) dynamic partial reconfiguration (DPR) of the CGRA for higher resource utilization by allowing fast switching between applications and partitioning resources between simultaneous applications; 2) streaming memory controllers supporting affine access patterns for efficient mapping of dense linear algebra; and 3) low-overhead transcendental and complex arithmetic operations. The physical design of Amber features a unique clock distribution method and timing methodology to efficiently layout its hierarchical and tile-based design. Amber achieves a peak energy efficiency of 538 INT16 GOPS/W and 483 BFloat16 GFLOPS/W. Compared with a CPU, a GPU, and a field-programmable gate array (FPGA), Amber has up to 3902 $\times $ , 152 $\times $ , and 107 $\times $ better energy-delay product (EDP), respectively.