Cell-aware analysis for small-delay effects and production test results from different fault models
Cell-aware analysis for small-delay effects and production test results from different fault models
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针对不同故障模型的小延迟效应和生产测试结果的单元感知分析
DOI：
10.1109/test.2011.6139151
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
J. Rivers
中科院分区：
文献类型：
--
作者：
F. Hapke;J. Schlöffel;W. Redemund;Andreas Glowatz;J. Rajski;Michael Reese;J. Rearick;J. Rivers
本文重点介绍了一种新的方法，以显着提高总体缺陷覆盖率的CMOS为基础的设计，最终目标是消除任何系统级测试。该方法描述了用于检测由单元内部电阻桥引起的单元内部小延迟缺陷的图案生成流程。结果已经在1，900个32 nm技术的库细胞上进行了评估。第一个生产测试结果，从评估额外的缺陷检测实现了不同的故障模型上的45纳米设计。
This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.