Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation
Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation
复制标题
在硅后验证期间自动选择用于位翻转检测的断言
DOI：
10.1109/tcad.2016.2538087
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发表时间：
2016
影响因子：
2.9
通讯作者：
N. Nicolici
中科院分区：
文献类型：
--
作者：
Pouya Taatizadeh;N. Nicolici
硅后验证涉及错误的检测和诊断，由于硅前验证中现有的限制，这些错误逃逸到硅原型上，需要在投入大批量制造之前修复。由于器件模型的精度不够，因此在硅前阶段特别难以捕获由串扰或功率下降等引起的电气错误，而器件模型的精度通常会与仿真时间进行权衡。电压域数量的增加进一步加剧了这一挑战，特别是在独特的电状态下激发细微误差的情况下。事实上，这些电引起的细微错误最常在逻辑域中表现为位翻转，并且据我们所知，没有系统方法来设计通用逻辑块的嵌入式硬件监视器，以低检测延迟检测位翻转。此外，与受益于明确定义和普遍接受的覆盖指标的硅前验证和制造测试不同，硅后验证结束时没有可以暗示信心的通用指标。为了实现这些目标，我们提出了一种依赖于设计不变量（断言）的方法，这些设计不变量根据检测位翻转的潜力进行排名。我们还引入了两个指标：位翻转覆盖率估计和触发器覆盖率估计，可用于评估所选断言的质量，以及一般而言，硅后验证过程的有效性。
Post-silicon validation deals with detection and diagnosis of errors that, due to existing limitations in pre-silicon verification, escape to the silicon prototypes and need to be fixed before committing to high-volume manufacturing. Electrical errors, such as those caused by cross-talk or power droops, are particularly difficult to catch during the pre-silicon phase because of the insufficient accuracy of device models, which is often traded-off against simulation time. This challenge is further aggravated by the rising number of voltage domains, especially if subtle errors are excited in unique electrical states. In fact these electrically-induced subtle errors most commonly manifest in the logic domain as bit-flips and, to the best of our knowledge, there are no systematic methods for designing embedded hardware monitors for generic logic blocks that can detect bit-flips with low detection latency. Moreover, unlike pre-silicon verification and manufacturing test that benefit from well-defined and universally accepted coverage metrics, there is no generic metric from which confidence can be implied at the end of post-silicon validation. Toward these goals, we present a method that relies on design invariants (assertions) that are ranked based on their potential to detect bit-flips. We also introduce two metrics bit-flip coverage estimate and flip-flop coverage estimate that can be used to assess the quality of the selected assertions, and, in general, the effectiveness of the post-silicon validation process.