A JFET-CMOS Technology for Low-Noise Sensor Interface Circuits
A JFET-CMOS Technology for Low-Noise Sensor Interface Circuits
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用于低噪声传感器接口电路的 JFET-CMOS 技术
DOI：
10.1541/ieejsmas.123.422
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
M. Ishida
中科院分区：
文献类型：
--
作者：
H. Takao;R. Asaoka;K. Sawada;S. Kawahito;M. Ishida
本文介绍了可集成在CMOS传感器接口电路中的结场效应晶体管（JFET）的制作工艺和器件特性。JFET适用于CMOS（运算）放大器，在传感器接口电路中实现极低噪声的前端放大器。它是在CMOS器件中由隔离的p阱区形成的。标准CMOS技术的额外工艺是一个光刻工艺和两个离子注入工艺。利用能量为150kev的磷离子注入，在JFET中形成n型通道，连接n+源极和漏极。然后用能量为30kev的硼进行浅离子注入形成p型顶栅区。制备的JFET器件具有良好的跨导性和低漏极电导性，适合用于模拟放大器。对制备的JFET的噪声功率谱进行了评价，并与n-MOSFET和p-MOSFET进行了比较。因此，JFET在1 kHz以下的噪声谱远低于CMOS器件。由于许多物理传感器的信号带宽都在低频，因此该器件可以作为低噪声传感器接口电路的关键器件应用于基于cmos的前端放大器中。
In this paper, fabrication technology and device characteristics of junction field effect transistor (JFET) which can be integrated in CMOS sensor interface circuits are presented. The JFET is applicable to CMOS (operational) amplifiers to realize a very low-noise front-end amplifier in sensor interface circuits. It is formed with isolated p-well area in CMOS device. Extra processes to a standard CMOS technology are one photolithography process and two ion-implantation processes. N-type channel in JFET is formed by deep ion-implantation of phosphorous with energy of 150 keV to connect n+ source and drain regions. After that, p-type top gate region is formed by shallow ion-implantation of borron with energy of 30 keV. Fabricated JFET devices showed enough transconductance and low drain conductance, which are suitable to use them in analog amplifiers. Noise power-spectrum of the fabricated JFET was evaluated, and compared with n-MOSFET and p-MOSFET. As a result, noise-spectrum of JFET below 1 kHz was much lower than that of CMOS devices. Since many physical sensors have their signal bandwidth in low frequency band, this JFET device can be utilized in CMOS-based front-end amplifiers as the key device of low-noise sensor interface circuits.