A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS
复制标题
采用 14nm CMOS 的输出电平转换稳定技术的 1.5GS/s 8b 流水线 SAR ADC
DOI:
10.1109/cicc48029.2020.9075942
复制
发表时间:
2020
期刊:
影响因子:
--
通讯作者:
S. Palermo
中科院分区:
文献类型:
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作者:
Yuanming Zhu;Shengchang Cai;Shiva Kiran;Yang;Po;S. Hoyos;S. Palermo
A single channel 1.5GS/s 8-bit pipelined-SAR ADC utilizes a novel output level shifting (OLS) settling technique to reduce the power and enable low-voltage operation of the dynamic residue amplifier. The ADC consists of a 4-bit first stage and a 5-bit second stage, with 1-bit redundancy to relax the offset, gain, and settling requirements of the first stage. Employing the OLS technique allows for an inter-stage gain of ~4 from the dynamic residue amplifier with a settling time that is only 28% of a conventional CML amplifier. The ADC's conversion speed is further improved with the use of parallel comparators in the two asynchronous stages. Fabricated in a 14nm FinFET technology, the ADC occupies 0.0013mm2 core area and operates with a 0.8V supply. 6.6-bit ENOB is achieved at Nyquist while consuming 2.4mW, resulting in an FOM of 16.7fJ/conv.-step.
DOI:
10.1109/cicc53496.2022.9772868
发表时间:
2022
期刊:
2022 IEEE Custom Integrated Circuits Conference (CICC
影响因子:
--
作者:
Zhu, Yuanming;Gomez Diaz, Julian Camilo;Kumar Kaile, Srujan;Yi, II-Min;Liu, Tong;Hoyos, Sebastian;Palermo, Samuel
通讯作者:
Palermo, Samuel
DOI:
10.1109/cicc53496.2022.9772785
发表时间:
2022
期刊:
2022 IEEE Custom Integrated Circuits Conference (CICC
影响因子:
--
作者:
Zhu, Yuanming;Liu, Tong;Kaile, Srujan Kumar;Kiran, Shiva;Yi, II-Min;Liu, Ruida;Gomez Diaz, Julian Camilo;Hoyos, Sebastian;Palermo, Samuel
通讯作者:
Palermo, Samuel