A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications
复制标题
采用 65nm 超低功耗 CMOS 的 1.1GHz 12μA/Mb 漏电流 SRAM 设计，具有适用于移动应用的集成漏电流减少功能
DOI：
10.1109/isscc.2007.373425
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
M. Bohr
中科院分区：
文献类型：
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作者：
Yih Wang;H. Ahn;U. Bhattacharya;T. Coan;F. Hamzaoglu;W. Hafez;C. Jan;P. Kolar;S. Kulkarni;Jie;Yong;I. Post;Liqiong Wei;Yih Zhang;Kevin Zhang;M. Bohr
在一个超低功耗的8 M 65 nm CMOS芯片上实现了一个低功耗高速SRAM宏，用于移动的应用。1 Mb宏具有0.667μm2低泄漏存储单元，工作电压为0.5V至1.2V。它的工作频率为1.1 GHz，1.2V，250 MHz，0.7V。在数据保持电压为0.5V时，漏电流降至12μA/Mb。在保持电压下，采用集成泄漏减少方案时，SRAM阵列的实测位单元泄漏为~ 2 pA/B。
A low-power high-speed SRAM macro is implemented in an ultra-low-power 8M 65nm CMOS for mobile applications. The 1Mb macro features a 0.667μm2 low-leakage memory cell and operates with supply voltage from 0.5V to 1.2V. It operates at a frequency of 1.1 GHz at 1.2V and 250MHz at 0.7V. Leakage is reduced to 12μA/Mb at the data retention voltage of 0.5V. The measured bitcell leakage from the SRAM array is ~2pA/b at retention voltage with integrated leakage reduction schemes.