Pinning Fault Mode Modeling for DWM Shifting
Pinning Fault Mode Modeling for DWM Shifting
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DOI：
10.1109/tcsii.2022.3161594
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发表时间：
2022-03
期刊：
影响因子：
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通讯作者：
Kawsher A. Roxy;Stephen Longofono;Sébastien Olliver;S. Bhanja;A. R. U. O. Florida;U. Pittsburgh
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文献类型：
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作者：
Kawsher A. Roxy;Stephen Longofono;Sébastien Olliver;S. Bhanja;A. R. U. O. Florida;U. Pittsburgh
为了实现更高的密度和更低的能量而进行的极端扩展继续增加内存故障的概率。对于域壁(DW)存储器，当将域与接入点对齐时会出现未对齐故障。作为一种以前研究较少的移位故障，钉扎故障可能是由于具有制造缺陷的缺口引起的钉扎电势分布不均匀而导致的。这种不均匀会在电流引起的DW运动中钉住一面墙。这份简报提供了一个几何变化的模型，该模型改变了缺口的宽度、深度和曲率变化，它们对临界移位电流的影响，以及由此对DW存储系统故障率的影响的研究。由于5%的变化而导致的有效临界移位电流的增加预测钉扎故障率在每移位10-8数量级。这导致DW存储系统的平均故障时间(MTTF)约为2s，并且需要多位纠错以实现合理的系统寿命。
Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability of memory faults. For domain wall (DW) memories, misalignment faults arise when aligning domains with access points. A previously understudied type of shifting fault, a pinning fault may occur due to non-uniform pinning potential distribution caused by notches with fabrication imperfections. This non-uniformity can pin a wall during current-induced DW motion. This brief provides a model of geometric variations varying width, depth, and curvature variations of a notch, their impacts on the critical shift current, and a study of the resulting impact on fault rates of DW memory systems. An increase in the effective critical shift current due to 5% variation predicts a pinning fault rate on the order of 10-8 per shift. This results in a mean-time-to-failure (MTTF) of circa 2s for a DW memory system and requires multi-bit error correction for achieving reasonable system lifetimes.