Timing Violation Induced Faults in Multi-Tenant FPGAs
Timing Violation Induced Faults in Multi-Tenant FPGAs
复制标题
多租户 FPGA 中时序违规引发的故障
DOI：
10.23919/date.2019.8715263
复制
发表时间：
2019
期刊：
影响因子：
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通讯作者：
Mirjana Stojilović
中科院分区：
文献类型：
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作者：
Dina G. Mahmoud;Mirjana Stojilović
FPGA已经进入云端，允许用户远程访问最先进的可重新配置结构，并实现他们的自定义加速器。由于FPGA足够大，可以容纳多个独立的设计，因此多租户用户场景可能很快就会在云计算环境中流行起来。然而，FPGA的共享使用引起了安全问题。最近发现的用于多租户FPGA设置的硬件特洛伊木马以拒绝服务攻击、电源侧信道攻击和串扰侧信道攻击为目标。在这项工作中，我们提出了一种攻击方法，导致时序约束违反多租户FPGA设置。这种类型的攻击是非常危险的，因为定时故障的后果是暂时的错误，通常不可能注意到。我们演示了一组自定时的真随机数发生器（STRNG），经常用于加密应用的攻击。当发起攻击时，STRNG输出变得有偏差，并且无法通过随机性测试。然而，在攻击之后，STRNG恢复并继续生成随机比特。
FPGAs have made their way into the cloud, allowing users to gain remote access to the state-of-the-art reconfigurable fabric and implement their custom accelerators. Since FPGAs are large enough to accommodate multiple independent designs, the multi-tenant user scenario may soon be prevalent in cloud computing environments. However, shared use of an FPGA raises security concerns. Recently discovered hardware Trojans for use in multi-tenant FPGA settings target denial-of-service attacks, power side-channel attacks, and crosstalk side-channel attacks. In this work, we present an attack method for causing timing-constraints violation in the multi-tenant FPGA setting. This type of attack is very dangerous as the consequences of timing faults are temporary errors, which are often impossible to notice. We demonstrate the attack on a set of self-timed true random number generators (STRNGs), frequently used in cryptographic applications. When the attack is launched, the STRNG outputs become biased and fail randomness tests. However, after the attack, STRNGs recover and continue generating random bits.