Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits
Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits
复制标题
细粒度流水线异步数据路径电路的时序约束的生成和验证
DOI：
10.1109/async.2002.1000301
复制
发表时间：
2002
期刊：
影响因子：
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通讯作者：
T. Nanya
中科院分区：
文献类型：
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作者：
Metehan Özcan;Masashi Imai;T. Nanya
时序分析是验证数字电路中时序约束的一种方法。异步电路的局部完成电路为时序分析带来了新的问题，这些电路在电路中产生周期，需要特殊处理。本文详细研究了细粒度流水线异步数据通路电路中的约束条件，并提供了一个自动生成和验证这些约束条件的工具环境，沿着给出了一些示例布局结果。
Timing analysis is a method for verification of timing constraints in a digital circuit. Asynchronous circuits bring new concerns for timing analysis with their local completion circuits, which generate cycles in the circuit and require special handling. In this paper constraints in fine grain pipelined asynchronous data-path circuits are examined in detail and a tool environment for automatic generation and verification of these constraints are presented along with some sample layout results.