CACTI 5 . 1
CACTI 5 . 1
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发表时间：
2008
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通讯作者：
Shyamkumar Thoziyoor;Naveen Muralimanohar;J. Ahn;Norman P. Jouppi
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作者：
Shyamkumar Thoziyoor;Naveen Muralimanohar;J. Ahn;Norman P. Jouppi
CACTI 5.1是CACTI 5的一个版本，修复了CACTI 5.0中的一些小错误。CACTI 5是CACTI工具的最新主要修订版，用于对高速缓存和其他存储器的动态功耗、访问时间、面积和泄漏功耗进行建模。CACTI 5包括了许多对CACTI 4的重大改进。首先，随着制造技术进入深亚微米时代，器件和工艺参数缩放已变得非线性。为了更好地模拟这一点，CACTI 5中的基本技术建模已从原始CACTI 0.8微米技术的简单线性缩放更改为基于ITRS路线图的模型。第二，嵌入式DRAM技术已经从一些供应商变得可用，并且存在对具有现代芯片多处理器的商品DRAM的3D堆叠的兴趣。作为另一个主要的增强，CACTI 5增加了对DRAM存储器的建模支持。第三，为了支持上述重大的技术建模变化，并实现SRA M和DRAM技术的公平比较，CACTI代码库已被广泛重写，以变得更加模块化。与此同时，各种电路假设已被更新，以更符合现代设计实践。最后，nume rous错误修复和小功能添加已经完成。例如，CACTI假定的该高速缓存组织现在以图形方式输出，以帮助用户理解CACTI生成的输出。
CACTI 5.1 is a version of CACTI 5 fixing a number of small bugs in CACTI 5.0. CACTI 5 is the latest major revision of the CACTI tool for modeling the dynamic power, ac cess time, area, and leakage power of caches and other memories. CACTI 5 includes a number of major improvements ov er CACTI 4. First, as fabrication technologies enter the deep-submicron era, device and process parameter scaling has become non-linear. To better model this, the base technology modeling in CACTI 5 has been changed from sim ple linear scaling of the original CACTI 0.8 micron technology to models based on the ITRS roadmap. Second, embe dded DRAM technology has become available from some vendors, and there is interest in 3D stacking of commodi ty DRAM with modern chip multiprocessors. As another major enhancement, CACTI 5 adds modeling support of DRAM mem ories. Third, to support the significant technology modeling changes above and to enable fair comparisons of SRA M and DRAM technology, the CACTI code base has been extensively rewritten to become more modular. At the sa me time, various circuit assumptions have been updated to be more relevant to modern design practice. Finally, nume rous bug fixes and small feature additions have been made. For example, the cache organization assumed by CACTI is now o utput graphically to assist users in understanding the output generated by CACTI.