Custom enhancements to networked processor templates
Custom enhancements to networked processor templates
复制标题
网络处理器模板的自定义增强功能
DOI：
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
W. Luk
中科院分区：
文献类型：
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作者：
T. Todman;W. Luk
处理器模板是设计FPGA技术的一种行之有效的方法，通过将其简化为选择模板并为其编写软件来简化实施任务，同时避免了对硬件设计经验的需求，并绕过了FPGA设计工具的安装和执行。网络处理器模板允许设计人员通过覆盖处理器网络来实现可扩展的并行性，同时保持使用处理器模板的简单性。本文提出了技术，以提高网络处理器模板的性能，通过添加自定义指令的处理器在网络中。已经开发了一种方法来系统地选择设计的部分以实现为定制指令。还设计了性能和面积模型，以允许预测针对特定FPGA的设计的性能和面积使用，从而在实现之前探索设计权衡。所提出的方法已在包括N体模拟和耗散粒子动力学在内的各种应用中进行了评估，证明了其基于针对最先进FPGA的自定义指令提供硬件加速的潜力。
Processor templates are a well-established way to design for FPGA technology, easing the task of implementation by reducing it to choosing a template and writing software for it – while avoiding the need for hardware design experience and circumventing the installation and execution of FPGA design tools. Networked processor templates allow designers to achieve scalable parallelism by covering a network of processors, while retaining the simplicity of using processor templates. This paper proposes techniques to improve the performance of networked processor templates, by adding custom instructions to processors in the network. An approach has been developed to systematically choose parts of a design to implement as custom instructions. Performance and area models have also been devised to allow the prediction of performance and area usage of a design targeting a particular FPGA, enabling design trade-offs to be explored prior to implementation. The proposed approach has been evaluated on various applications including N-body simulation and dissipative particle dynamics, demonstrating its potential of delivering hardware acceleration based on custom instructions targeting state-of-the-art FPGAs.