Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization

Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization
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DOI:
10.1109/ted.2014.2363117
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发表时间:
2015-06
影响因子:
3.1
通讯作者:
A. Asenov;B. Cheng;Xingsheng Wang;A. Brown;C. Millar;C. Alexander;S. Amoroso;J. B. Kuang;S. Nassif
A. Asenov;B. Cheng;Xingsheng Wang;A. Brown;C. Millar;C. Alexander;S. Amoroso;J. B. Kuang;S. Nassif
中科院分区:
工程技术2区
文献类型:
--
作者:
A. Asenov;B. Cheng;Xingsheng Wang;A. Brown;C. Millar;C. Alexander;S. Amoroso;J. B. Kuang;S. Nassif

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在本文中,我们在基于14纳米互补金属氧化物半导体鳍式场效应晶体管(FinFET)/静态随机存取存储器(SRAM)模拟的设计技术协同优化(DTCO)中使用了一种自动化工具流程,该流程包括工艺引起的和固有统计变异性。我们使用22纳米FinFET互补金属氧化物半导体技术来说明对工艺引起的鳍形状变化的敏感性,并以此引出本文。我们进行了预测性技术计算机辅助设计(TCAD)模拟,以便在硅片之前评估晶体管性能。根据系综蒙特卡罗模拟结果校准的漂移 - 扩散模拟被用于探索工艺和统计变异性空间。这是通过工具流程的自动化和数据集处理实现的。我们详细研究了工艺和统计变异性之间的相互作用。我们使用一种两阶段紧凑模型策略来捕捉工艺和统计变异性之间的相互作用。为了闭合DTCO循环,我们详细研究了基于FinFET的SRAM设计中静态噪声容限和写入噪声容限对单元设计参数和变异性的敏感性。
In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details.