MOS capacitance measurements for high-leakage thin dielectrics
MOS capacitance measurements for high-leakage thin dielectrics
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DOI：
10.1109/16.772500
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发表时间：
1999-07-01
影响因子：
3.1
通讯作者：
Hu, CM
中科院分区：
文献类型：
--
作者：
Yang, KJ;Hu, CM
随着 MOS 器件中氧化物厚度降至 2.5 nm 以下，串联和并联寄生电阻在电容电压 (C-V) 测量中变得非常重要。提出了一种新技术，该技术允许从两个频率的阻抗测量中准确提取与频率无关的器件电容。该技术已针对 1.7 nm SiO2 电容器进行了演示。
As oxide thickness is reduced below 2.5 nm in MOS devices, both series and shunt parasitic resistances become significant in capacitance-voltage (C-V) measurements. A new technique is presented which allows the frequency-independent device capacitance to be accurately extracted from impedance measurements at two frequencies. This technique is demonstrated for a 1.7 nm SiO2 capacitor.