Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
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DOI：
10.1587/transele.e93.c.270
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发表时间：
2010-03
期刊：
影响因子：
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通讯作者：
Xiao Peng;Zhixiang Chen;Xiongxin Zhao;F. Maehara;S. Goto
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文献类型：
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作者：
Xiao Peng;Zhixiang Chen;Xiongxin Zhao;F. Maehara;S. Goto
由于现代无线通信系统中的结构化准循环低密度奇偶校验（QC-LDPC）码包含多种码率、不同的块长度和相应的不同大小的奇偶校验矩阵（PCM）子矩阵，因此需要可重构的LDPC译码器，并且需要置换网络来适应任意的输入数（IN）和移位数（SN）进行循环移位。提出了一种基于Banyan网络的可重构QC-LDPC译码器的置换网络结构。证明了当IN为2的幂时，Banyan网络具有循环移位的无阻塞性，并给出了控制信号的产生算法。通过引入旁路网络，提出了任意IN和SN的无阻塞方案。此外，本文还给出了控制信号发生器的硬件设计，大大降低了硬件复杂度和延迟。在TSMC 0.18 μm库上的综合结果表明，该置换网络的面积为0.5 46 mm 2，频率为2 92 MHz.
Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 μm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm 2 and the frequency of 292 MHz.