An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems
An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems
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DOI：
10.1109/mwscas.2006.382032
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发表时间：
2006-08
期刊：
影响因子：
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通讯作者：
M. Myjak;J. Delgado-Frías;S. Jeon
中科院分区：
文献类型：
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作者：
M. Myjak;J. Delgado-Frías;S. Jeon
深度流水线系统需要具有低延迟和低功耗的触发器。通常，触发器必须向后续逻辑提供反相和非反相信号。同时生成两个输出可以通过均衡最坏情况的延迟来提高性能。在本文中，我们提出了一种用于深度流水线系统的新型差分触发器。该电路使用交叉耦合的p晶体管作为上拉器件以实现高能效。我们采用 90 纳米 CMOS 技术对设计进行了模拟，以确定延迟和功耗。然后，我们对其他四个产生对称输出的差分触发器重复了分析。所提出的设计实现了五种替代方案中最佳的功率延迟乘积。
Deeply pipelined systems require flip-flops with low latency and power consumption. Often, the flip-flop must supply both inverted and non-inverted signals to subsequent logic. Generating both outputs at the same time improves performance by equalizing the worst-case delays. In this paper, we present a novel differential flip-flop for deeply pipelined systems. The circuit uses cross-coupled p-transistors as pull-up devices to achieve high energy efficiency. We simulated the design in 90-nm CMOS technology to determine the delay and power consumption. We then repeated the analysis with four other differential flip-flops that produce symmetric outputs. The proposed design achieves the best power-delay product of the five alternatives.