A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer
复制标题
具有嵌入式 IIR 均衡器的基于 12.8 Gbaud ADC 的有线接收器
DOI：
10.1109/jssc.2019.2956395
复制
发表时间：
2020
影响因子：
5.4
通讯作者：
M. Chen
中科院分区：
文献类型：
--
作者：
J. Nam;M. Chen
本文演示了一款基于模数转换器（ADC）的NRZ/PAM 4调制接收机，该接收机采用时间数字转换器（TDC）辅助的多位/周期异步逐次逼近寄存器（SAR）ADC，内置IIR均衡滤波器，由具有有源增益的差分源极跟随器驱动。它重新利用时间交错（TI）ADC的现有采样网络，并集成有源Gm-C积分器，以形成可调IIR均衡器响应。该原型是在65 nm的互补金属氧化物半导体（CMOS）制造，并实现了2.43 pJ/B的效率使用12.8 Gbuad的PAM 4调制方案。八路TI ADC测量4.84峰值有效位数，功耗为36.3 mW，占用0.24 mm 2内核面积。
This article demonstrates an analog-to-digital converter (ADC)-based receiver for NRZ/PAM4 modulation, featuring a time-to-digital converter (TDC)-assisted multi-bit/cycle asynchronous successive approximation register (SAR) ADC with embedded IIR equalization filter driven by the differential source followers with an active gain. It re-uses the existing sampling network of time-interleaved (TI) ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65-nm complementary metal–oxide–semiconductor (CMOS) and achieves an efficiency of 2.43-pJ/b using the 12.8-Gbuad PAM4 modulation scheme. The eight-way TI ADC measures 4.84 peak effective number of bit with power consumption of 36.3 mW while occupying 0.24 mm2 core area.