Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration
Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration
复制标题
使用基于转移堆叠的芯片到晶圆 3D 集成实现最后通孔 TSV 形成的自组装和静电载体技术
DOI：
10.1109/ted.2017.2767598
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发表时间：
2017
影响因子：
3.1
通讯作者：
and Mitsumasa Koyanagi
中科院分区：
文献类型：
--
作者：
Hideto Hashiguchi ;Takafumi Fukushima ;Hiroyuki Hashimoto;Ji-Cheol Bea;Mariappan Murugesan;Hisashi Kino; Tetsu Tanaka;and Mitsumasa Koyanagi
自组装和静电（SAE）载体技术是为高精度和高吞吐量的芯片到晶圆3-D集成开发的。在本文中，水面张力驱动芯片组装与静电粘附相结合，以保持高的对准精度所获得的毛细管自组装过程。自组装芯片可以通过静电粘附牢固地固定在SAE载体晶片上，然后，芯片可以通过放电容易地从载体分离，并利用临时粘合剂转移到另一载体。本文介绍了芯片夹紧力和电气可靠性的SAE载体上的芯片的影响是3-D堆叠在芯片到晶圆配置。采用基于SAE载体的最后通孔三维集成工艺，演示了单晶硅通孔的形成。实验结果表明，SAE载体比无静电粘附的传统载体保持更高的芯片对准精度。
A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.