A new approach for selecting inputs of logic functions during debug

A new approach for selecting inputs of logic functions during debug
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调试期间选择逻辑功能输入的新方法

DOI:
10.1109/isqed.2017.7918311
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发表时间:
2017
期刊:
2017 18th International Symposium on Quality Electronic Design (ISQED)
影响因子:
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通讯作者:
Fujita Masahiro
Fujita Masahiro
中科院分区:
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文献类型:
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作者:
Gharehbaghi Amir Masoud;Fujita Masahiro

文献摘要

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可编程逻辑函数涉及找到一些内部节点的功能,以便根据给定的规范,它们的功能变得正确。在某些情况下,需要不同的新输入,这些内部节点才能纠正功能。在本文中,我们提出了一种有效的方法来选择输入的内部节点在调试过程中,这样的正确性得到保证。我们的方法有一种新的不同的调试方法,专注于找到函数的输入,而不显式地尝试找到新函数。这是通过迭代求解SAT问题来完成的,直到我们找到输入。在ITC'99基准测试上的实验结果表明了该方法的有效性。结果表明,与以前的方法相比,平均减少了30%以上的SAT问题的数量,以及减少了85%以上的调试时间。
Debugging logic functions involves finding the function of some of the internals nodes such that their functionality becomes correct, according to the given specification. In some cases, different new inputs are required for those internal nodes to be able to correct the functionality. In this paper, we propose an efficient method for selecting inputs of internal nodes during debug such that correction is guaranteed. Our method has a new different approach for debugging that focuses on finding the inputs of the functions without explicitly trying to find the new functions. This is done by iteratively solving SAT problems until we find the inputs. Our experimental results on ITC'99 benchmarks show the efficiency and effectiveness of our approach. The results show more than 30% reduction in the number of SAT problems to be solved as well as more than 85% reduction in debug time, on average, compared to the previous methods.