Spectroscopic performance improvement of SOI pixel detector for X-ray astronomy by introducing Double-SOI structure
Spectroscopic performance improvement of SOI pixel detector for X-ray astronomy by introducing Double-SOI structure
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DOI：
10.1088/1748-0221/15/11/p11001
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发表时间：
2020-11
影响因子：
1.3
通讯作者：
A. Takeda;K. Mori;Y. Nishioka;K. Fukuda;M. Yukumoto;T. Hida;T. Tsuru;T. Tanaka;H. Uchida;H. Hayashi;S. Harada;T. Okuno;K. Kayama;Y. Arai;I. Kurachi;T. Kohmura;K. Hagino;K. Negishi;K. Oono;K. Yarita;H. Matsumura;S. Kawahito;K. Kagawa;K. Yasutomi;S. Shrestha;S. Nakanishi;H. Kamehama
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文献类型：
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作者：
A. Takeda;K. Mori;Y. Nishioka;K. Fukuda;M. Yukumoto;T. Hida;T. Tsuru;T. Tanaka;H. Uchida;H. Hayashi;S. Harada;T. Okuno;K. Kayama;Y. Arai;I. Kurachi;T. Kohmura;K. Hagino;K. Negishi;K. Oono;K. Yarita;H. Matsumura;S. Kawahito;K. Kagawa;K. Yasutomi;S. Shrestha;S. Nakanishi;H. Kamehama
本文报道了一种用于X射线天文学的绝缘体上硅（SOI）像元探测器的光谱性能的改善，通过引入双SOI（D-SOI）结构。针对X射线天文台的应用，我们研制了一系列基于SOI像素技术的单片有源像素传感器，称为“XRPIXs”。D-SOI结构的优点在于它可以抑制感测节点和电路层之间的寄生电容，由于寄生电容，在具有单SOI（S-SOI）结构的常规XRPIX中不能增加闭环增益。与S-SOI XRPIX相比，D-SOI XRPIX的闭环增益增加了一倍。读出噪声有效地降低到33%（16 e−（rms）），6.4 keV的能量分辨率提高了1.7倍（FWHM为290 eV）。寄生电容的抑制也定量评估的基础上，从布局的电容提取模拟的结果。该评估为进一步降低读出噪声提供了设计指导。
This paper reports the spectroscopic performance improvement of the silicon-on-insulator (SOI) pixel detector for X-ray astronomy, by introducing a double-SOI (D-SOI) structure. For applications in X-ray astronomical observatories, we have been developing a series of monolithic active pixel sensors, named as “XRPIXs,” based on SOI pixel technology. The D-SOI structure has an advantage that it can suppress a parasitic capacitance between the sensing node and the circuit layer, due to which the closed-loop gain cannot be increased in our conventional XRPIXs with a single-SOI (S-SOI) structure. Compared to the S-SOI XRPIX, the closed-loop gain is doubled in the D-SOI XRPIX. The readout noise is effectively lowered to 33% (16 e− (rms)), and the energy resolution at 6.4 keV is improved by a factor of 1.7 (290 eV in FWHM). The suppression of the parasitic capacitance is also quantitatively evaluated based on the results of capacitance extraction simulation from the layout. This evaluation provides design guidelines for further reduction of the readout noise.