Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs
Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs
复制标题
具有 FIR 反馈 DAC 的宽带单位连续时间 $DeltaSigma$ 调制器的设计技术
DOI：
10.1109/jssc.2012.2217871
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发表时间：
2012
影响因子：
5.4
通讯作者：
S. Pavan
中科院分区：
文献类型：
--
作者：
Pradeep Shettigar;S. Pavan
我们给出了具有FIR反馈DAC的单比特连续时间Δ-Σ调制器（CTDSM）的设计考虑。这些调制器具有多位调制器的低抖动灵敏度和高线性特性，同时使用简单的一位量化器，从而结合了单位和多位操作的优点。我们提出了一种方法来补偿环路的延迟引入FIR-DAC。我们的架构和电路技术的功效是证明了从调制器的测量结果，实现约71 dB的SNDR在36 MHz的带宽，而消耗只有15 mW的1.2 V电源。CTDSM采用90 nm CMOS工艺实现，采样速度为3.6 GS/s，其品质因数（FoM）为72.7 fJ/lvl，占用面积为0.12 mm 2。
We give design considerations for single-bit continuous-time Delta-Sigma modulators (CTDSMs) with FIR feedback DACs. These modulators have the low jitter sensitivity and high linearity properties characteristic of a multibit modulator, while using a simple one-bit quantizer, thereby combining the advantages of single-bit and multibit operation. We propose a method to compensate the loop for the delay introduced by the FIR-DAC. The efficacy of our architectural and circuit techniques is borne out by measurement results from a modulator that achieves about 71-dB SNDR in a 36-MHz bandwidth while consuming only 15 mW from a 1.2-V supply. Implemented in a 90-nm CMOS process and sampling at 3.6 GS/s, the CTDSM has a figure of merit (FoM) of 72.7 fJ/lvl, while occupying 0.12 mm2.